On-chip multiprocessing systems are becoming increasingly common, but it is a challenge to design and customise them to meet the constraints of a particular application domain. As the number of processing cores on a single silicon die increases, so does the importance of the interprocessor communication infrastructure. Networks-on-Chip (NoCs) are considered a promising architectural template for on-chip communication, allowing large numbers of processors to exchange data over a shared multi-hop network implemented in the silicon die. However, the design space of NoCs is very large, including multiple alternatives on topology, routing, flow control and arbitration. System designers must be able to evaluate the impact of each of such design choices on application specific constraints such as communication latency and power consumption. Furthermore, the mapping of application tasks onto the platform can also have a large impact on those metrics. This course will cover some of the basics of NoC architectures and will address the research challenges of evaluating and tuning a multiprocessor platform to better fit the requirements of specific applications.