1. Gert Jervan, Tallinn University of Technology
System level design for dependability and reliability PDF
Technology scaling into subnanometer range will have impact on the manufacturing yield and quality. At the same time complexity and communication requirements of systems-on-chip (SoC) are increasing, thus making a SoC designer goal to design a fault-free system a very difficult task. Network-on-chip (NoC) has been proposed as one of the alternatives to solve some of the on-chip communication problems and to address dependability on various levels of abstraction. This talk concentrates on system-level design issues of NoC-based systems. We will describe various methods proposed for NoC architecture analysis and optimization, and give an overview of different system-level fault tolerance methods. Finally, a short overview of a system-level design framework for performing design space exploration for dependable NoC-based systems will be presented.
2. Andreas Steininger, Vienna University of Technology
Clocking and Timing in Fault-Tolerant Systems on Chip PPTX
As a result of the tremendous level of integration enabled by modern VLSI technology, complete embedded systems can nowadays be implemented on a single chip, leading to so-called "Systems on Chip (SoC)". Typically these SoCs are structured in relatively independent functional modules that mutually exchange information to provide the overall function.
The clocking of these modules is becoming an increasingly challenging issue: The traditional approach of using the same central clock for all modules within the SoC is very efficient, but hard to implement in high-speed architectures. In my talk I will elaborate on this issue and present existing alternatives, such as the "globally asynchronous locally synchronous (GALS)" approach and completely asynchronous design, along with the related benefits and drawbacks.
Since SoCs are often applied in a safety-critical context, I will subsequently view the proposed clocking alternatives from a fault-tolerance point of view: Centrally clocked systems suffer from the clock being a single point of failure, while in GALS systems metastability becomes a problem. Finally, in fully asynchronous architectures it is hard to implement the usual redundancy concepts. I will spend some time discussing these issues in more depth. As a recent research result I will then present a clocking scheme called DARTS (Distributed Algorithms for Robust Tick Synchronization) that inherently generates a globally synchronized clock in a fault-tolerant distributed manner, and report on our experimental results with a chip-implementation of this approach.
3. Thomas Hollstein, Tallinn University of Technology
Scalable dependable SoC Architectures based on Networks-on-Chip
Nanoscaled silicon technologies are the enabling factor for the realisation of large and scalable System-on-Chip (SoC) Architectures. Increasing system complexity and decreased transistor geometries with increased parameter variations define a huge challenge for the design of reliable SoCs with an optimized manufacturing yield. In this presentation it will be shown, that the concept of using Networks-on-Chip as SoC communication architectures is a sustainable approach for the realisation of reliable and scalable SoC architectures. In the context of dependability, required NoC properties will be accentuated and illustrated using the example of the scalable XHiNoC architecture. Finally future developments and system integration issues will be outlined.
4. Peeter Ellervee, Tallinn University of Technology
Bottlenecks in Hardware Design and Design Automation (Hardware Synthesis: No Pain, No Gain) PDF
Design automation, including modeling and synthesis tools, have significantly increased designers productivity. For many years, hardware description languages have been used successfully as the input for synthesis tools. However, this has been done mostly at the register-transfer level. To increase their productivity, designers would like to work at higher levels but are the synthesis tools ready for that? Yes and no - all depends what is expected. To make it even more interesting, synthesis tools handle different constructs differently although the resulting hardware will function in the same way. This lecture will give an overview how to various constructs will be implemented depending on the used tools. In addition, some examples will be given how to optimize hardware without going into too low level details.
5. Heinrich Theodor Vierhaus, Brandenburg University of Technology, Cottbus
Self Repair Technology for Logic Circuits - Architecture, Overhead and Limitations PPT
Digital integrated circuits fabricated in nano-technologies suffer from fault effects, which were not known or insignificant in older technologies. Besides transient fault effect, there are specific mechanisms like metal migration or negative bias thermal instability (NBTI) and even dielectric breakdowns, which result in wear-out effects and early failure. Compensation these effects on top of transient faults by either coding or active redundancy is becoming prohibitively expensive. Therefore a repair mechanisms that can compensate permanent faults using "fresh" redundancy may become an attractive alternative. While such methods are frequently used for embedded memory blocks and for storage devices already, they are much more difficult to implement for non-regular or semi-regular logic. The tutorial shows feasible architectures for repair mechanisms in logic and arithmetic circuits. Cost, overhead and limitations are also discussed. On top of that, the concept of life-time extension by mechanisms of de-stressing is introduced. Finally, essential bottlenecks are shown that may limit repair mechanisms in general with respect to the manageable fault density.
6. Mario Schölzel, Brandenburg University of Technology, Cottbus
Self-testing and self-repairing processors PPT
Several effects in nano-scaled CMOS ICs will cause permanent faults, which may result in early life failures and wear out effects. This presentation shows methods to handle permanent faults in-the-field in programmable statically scheduled super-scalar processors. It starts with a simple hardware extension of the data path, and it is shown how this hardware extension can be emulated by a software routine, resulting in a pure software based self-repair approach. Finally, the software routine is refined in order to reduce the size of the components in the processor for which a permanent fault can be handled by the self-repair routine. By this, it is possible to handle multiple permanent faults without too much administration overhead.
7. Raimund Ubar, Tallinn University of Technology
Fault modeling and diagnosis in digital systems PPT
Rising design complexity and shrinking structures pose new challenges and growing attention to the problems of testing. The logical stuck-at fault model has been a long time the prevalent technique to handle formally physical defects in electronic systems. In today's systems, however, we have two difficulties when using this model: it is too complex because of the huge number of faults to be handled in systems, and it is inaccurate to represent real physical defects taking place in today's nanoelectronic circuits. The paradox is that the two difficulties are working against each other: when trying to represent the defects with less complex and higher level fault models the accuracy will even decrease, and vice versa, when trying to increase the accuracy of representing defects, the complexity of the fault model will increase. In this presentation, an overview about the fault models will be given. A novel approach of a general fault model called constraint based stuck-at fault model will be described and an introduction to higher level and hierarchical approaches to fault modeling will be given. The two most commonly used fault diagnosis paradigms - cause effect analysis and effect-cause analysis - along with their modifications are introduced and compared. A problem related to the traditional fault model based diagnosis is that the know-how about possible defects and faults is quickly getting obsolete, new failure mechanisms and defect types are continuously evolving with advances in fabrication process technology. This makes defect and fault-model based testing extremely difficult and inefficient. New directions to fault diagnosis without using fault models will be discussed.
7. Jaan Raik, Tallinn University of Technology
Techniques for automated localization and correction of design errors PPT
Increasing design costs are the main challenge facing the IC community today. Assuring the correctness of the design, i.e. verification, contributes to the major part of the problem. However, to date there has been little research into debug tools that diagnose and correct errors automatically. This presentation gives an overview of formal and simulation-based techniques that have been developed for automated debug. It focuses on latest repair methods that provide readable and small scale fixes to design errors. It will be shown that readability is not only important to the design engineer who interacts with the debug software but also provides higher quality repairs.