Pausible Clocking Based GALS Design and Its Applications in Digital System Integration - Xin Fan, IHP Microelectronics, Germany
Globally asynchronous locally synchronous (GALS) design has attracted intensive research attention during the last decade. Among the existing GALS design solutions, the pausible clocking scheme presents an elegant approach to address the synchronization issues in data transfer across clock regions with low overhead. In this talk we will report the recent progress in the optimal GALS design based on pausible clocking scheme. At the interface design level, the analysis and optimization of pausible clocking based GALS data link is presented, with the consideration for both high-throughput and high-reliability. At the system integration level, studies focus on the optimal partitioning strategy of GALS system for the area/power efficient and low EMI-noise digital design. A GALS design flow specific for applying the pausible clocking scheme is further developed. As the latest design case, a synchronous/GALS OFDM baseband transmitter (BB TX) chip, named Moonrake, was implemented using state-of-the-art 40-nm CMOS technology. Experimental results and comparison in the area, power and EMI properties between the Moonrake synchronous BB TX design and the GALS counterpart will be presented in the talk.
zamiaCAD: Under the Hood - Guenter Bartsch, zamiaCAD founder, Germany PDF
zamiaCAD is a modular and extensible platform for advanced hardware design, analysis, and research. After giving a short overview of zamiaCAD's features, we will dive into the algorithms and data structures behind them. We will shed some light on VHDL parsing and elaboration, give details about the data models used and look at some applications like signal tracing, simulation and common IDE tasks. We will also show how to make the data structures involved scale well for industrial-sized designs.
Advanced Application of Dynamic and Partial Reconfiguration - Michael Hübner, Karlsruhe Institute of Technology, Germany PDF
Dynamic and partial reconfiguration FPGAs is a well known technique for runtime adaptive system design. The technique enables to substitute parts of a configuration while other regions stay operative without any disturbance. The advantage is the fact, that the spatial and temporal partitioning can be exploited with the goal to increase the performance and to reduce the power consumption due to the re-use of chip area. This talk introduces a novel methodology to exploit this dynamic adaptation in processor cores, in order to adapt the microarchitecture in relation to the application requirements. Furthermore, the increased degree of freedom which is enabled through the approach for a novel quality of processors, called i-Core is described.
Dynamically Reconfigurable Resource Array - Ahmed Hemani, KTH, Kista, Sweden PDF
Dynamically Reconfigurable Resource Array (DRRA) is a Coarse Grain Reconfigurable Fabric that targets multiple achieving near ASIC like performance while retaining programmability. An overview of the architectural concept and methodology for programming DRRA are presented. Benefits and preliminary results are presented.
What Does It Take to Design Dependable Devices? - Jan Schmidt, Czech Technical University in Prague, Czech Republic PDF
The talk starts with the intuitive notion of dependability and builds more precise objectives on it, together with a terminological base. Then the methodology and tools used for dependability are compared with those for design. Ways to extend the classical redundancy insertion methods towards system level are presented, along with extended dependability modeling methods. For any analysis to be relevant, the underlying assumptions must be realistic. In dependability research, relevance is extremely important, yet relevant data are difficult to obtain. Therefore, experiments and measurements targeted on dependability models are presented.
[SHIFTED to the next event] Complex System Design and Debug - Rainer Dorsch, IBM, Germany
Designing modern computer systems is a complex and comprehensive task. I will briefly describe the architecture of a modern IBM System z computer, then I will talk about the challenges and techniques used in the design and debug phases of these system. I will emphasize on the system level design aspects in the various design phases. This starts at high-level design with performance modeling, covers the RTL design process, and the interface to physical design. Further firmware development and virtual prototyping using in firmware development is covered. Finally, I show that silicon debug is required for these kind of systems and give an overview of the techniques used.
[SHIFTED to the next event] Transaction Level Modeling: Emerging Methodology for System Design - Syed Saif Abrar, Intel, India
Modern day electronic products (e.g. handheld devices, digital TVs, etc) are expected to deliver ever increasing functionality at ever decreasing cost. Productivity of the SoC designers needs to cope up with the increasing system-design complexity. System design tasks, like exploration, development, verification, etc are no longer feasible at the current RTL level. Many methodologies, like prototyping, FPGAs, emulators, etc, have been proposed/used to overcome these challenges. Transaction Level Modeling (TLM) is an emerging methodology to address the needs of modern and futuristic SoCs. TLM encompasses any level that is above RTL, like algorithmic level, behavioral models, hardware/software co-development, etc. Focus of the TLM is more on the system-level functionality, rather than exact communication protocol between modules. This enables 100x simulation speedup than RTL, allowing system-level exploration, verification, software-development, etc on a PC. This talk will introduce the TLM methodology, discuss various abstraction levels (PV, LT, AT, CA), along with their applicability to various system-design use-cases. Being an emerging methodology, TLM has its own challenges that will be touched upon. Finally the applicability of TLM within industry will be discussed with examples.